Power Estimation of Switching Activity for Low – Power Implementation on FPGA

The FPGAs can be configured by the end-user to implement any digital system virtually, which may use millions of gates to be operated at few hundred MHz speed. Because of its reprogrammability, the FPGAs become very popular for the applications where prototyping and economic viability are of great concern. The state-of-the-art fabrication and manufacturing technologies are used to produce the current FPGAs, which comprise of high degree of integration and huge number of transistor count to make it suitable for today’s applications with high performance, but face a power consumption problem. Lower power consumption is a critical design issue in most embedded systems with CMOS technology, where logic switching is a significant factor affecting the system power consumption. The higher the switching frequency the larger the power consumed. This paper discusses the major power consumption sources in VLSI circuit with the primary focus on switching activity, its computation and its power estimation carried out by probabilistic approach.