Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Network

A fault-tolerant distributed decision fusion in the presence of sensor faults via Collaborative Sensor Fault Detection (CSFD) was used traditionally. CSFD scheme is proposed in which the results of a homogeneity test are used to identify the faulty nodes within the network such that their quantized messages can be filtered out when estimating the parameter of interest. The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented in an ASIC and included in a stand-alone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the Approximated Collaborative Sensor Fault Detection (ACSFD) scheme and its VLSI architecture. Sorting operation are required in ACSFD to find out four biggest faulty node indexes for subsequent usage for this purpose. we have implemented different sorting algorithm to evaluate the efficiency of the sorting network.