Implementation of Reconfigurable Redundant Radix-4 Arithmetic Co-Processor

This paper deals with the design and implementation of a Field Programmable Gate Array (FPGA) based co-processor called Redundant Radix-4 Arithmetic co-processor. In the proposed work different arithmetic operations addition, subtraction, complementation, multiplication, square, division left shift and right shift are implemented. These arithmetic operations are implemented using Redundant Radix-4 (RR-4) number system for achieving high speed. The binary numbers are converted to RR-4 and these numbers are used for arithmetic operations. This RR-4 number system will carry out the operations in parallel. Parallel addition of two m-digit redundant binary numbers can be performed in a same interval of time independent of m, without using propagated carry. The proposed co-processor is developed by set of Very High Speed Integrated Circuit Hardware Description Language (VHDL) modules for fast parallel arithmetic operations. The implementation is done through different stages of Xilinx Integrated Software Environment (ISE) 12.4 and physical verification is carried out on Virtex 5 XC5VLX110T Field Programmable Gate Array (FPGA). The simulation results of co-processor are observed using Xilinx ISim simulator. The co-processor is interfaced with the Chipscope Pro Virtual Input-Output (VIO) console, to enter data from the keyboard and to get back the result in VIO console window. This co-processor occupies area of 2281.52 μm2 and 407.848 MB of memory with switching power 1.02489371 mW.