Low Power and High Speed Clock Triggered Comparator Using 0.18μm Technology

In Digital Wireless Communication application, the design of Low Power and High Speed Analog to Digital Converter (ADC) is the need-of-the-day. This paper explores the design of low power and high speed comparator used in all available ADC architectures. This paper aims to design a CMOS comparator with a considerably high speed maintaining its low power consumption with clock as triggering input. The design has been simulated using 0.18 μm CMOS technology to provide better performance verification leading to low power dissipation, high speed and low propagation delay. Simulation results for its functionality have been verified using Cadence Virtuoso tool 6.1.3 version for better comparator results. This paper has been compared with the results of present earlier reported work, and obtained improvement in the present work. The designed comparator consumes 7.849 x 10-12 W of power dissipation from 1.8 v power supply and propagation delay is of 0.058 ns. The comparator layout occupies area is 4 x 11 μm2.