Power Reduction and Power Management in At-Speed Scan Based Testing Applied to SOC

The focal goal of this paper is to shrink power consumption for the duration of at speed scan based testing. In scan-based tests, power consumptions in both shift and capture phase may be drastically privileged than that in regular approach, which threaten circuits’ trustworthiness through manufacturing test. High power consumed during shift and capture phases upshot in structural smash up to silicon or flawed data transmit during manufacturing test. Prior X filling techniques diminish either shift power or capture power however not together. Work of fiction Proposed X filling technique that can dwindle both shift- and capture-power for the period of speed scan based testing. Further still more reduce power consumption by adding dynamic voltage scaling method with X-filling method.