VLSI Power Optimization Using Hybrid Logic Cells

Power is a major concern in today's design. The challenges faced in VLSI (Very Large Scale Integrated) circuits in sub micrometer technologies include increasing power dissipation and interconnect dominance. The pass transistor logic (PTL) family is an excellent choice for low power designs, but its use has been limited due to the lack of design automation tools. The work presents a design for low power and area synthesis. The development of a logic synthesis tool, designed specifically to work with a reduced set cell library consisting of a combination of pass logic and standard CMOS topologies is found to be more advantageous than the conventionally used CMOS logic design styles. Hence hybrid design styles are preferred. The processing technology (0.18um) enables the ease of design. This result in hybrid logic cells for standard cell based design environment.