Programmable Device Circuits and Systems

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A Survey on Single and Double Edge-Triggered Flip-Flops to Design Scan Flip-Flop Cell


Affiliations
1 Vellore Institute of Technology (VIT) University, Vellore, Tamil Nadu, India
2 School of Electronics Engineering, Vellore Institute of Technology (VIT) University, Vellore, Tamil Nadu, India
     

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This paper elucidates about different topologies of both SET&DET flip-flops and investigated under estimation of performance metrics like Power consumption, delay (D-Q), Area, Transistor Count, Number of Clocked Transistors, PDP and EDP extensively. Based on this survey a new low power, less area occupied, high performance Pulsed scan flip-flop cell is proposed.


Keywords

Dual Edge Triggered Flip-Flop, Flip-Flop, Low Power, Pulse Triggered Operation.
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  • A Survey on Single and Double Edge-Triggered Flip-Flops to Design Scan Flip-Flop Cell

Abstract Views: 249  |  PDF Views: 3

Authors

D. Satya Valibaba
Vellore Institute of Technology (VIT) University, Vellore, Tamil Nadu, India
S. Sivanantham
School of Electronics Engineering, Vellore Institute of Technology (VIT) University, Vellore, Tamil Nadu, India

Abstract


This paper elucidates about different topologies of both SET&DET flip-flops and investigated under estimation of performance metrics like Power consumption, delay (D-Q), Area, Transistor Count, Number of Clocked Transistors, PDP and EDP extensively. Based on this survey a new low power, less area occupied, high performance Pulsed scan flip-flop cell is proposed.


Keywords


Dual Edge Triggered Flip-Flop, Flip-Flop, Low Power, Pulse Triggered Operation.