Speed Optimized AES Algorithm on Re-Configurable Hardware

In recent days, the importance of security in IT sectors has been increased significantly. Advanced Encryption Standard (AES), is an approved cryptographic algorithm that can be used to protect electronic data. Nowadays, Most of secure transactions are occurring on smart phones, ATM transactions and other handheld devices. So that high speed algorithm to perform the same has become the need for recent days. For high speed performance in algorithm and to reduce unbreakable delay in combinational path then pipeline architecture is used. So that proposed work employs a s-box design based on pipeline Architecture synthesis and simulated on Modelsim Altera and also implemented on Altera DE-2 board. So this architecture employs a Boolean simplification of the truth table of the logic function with the aim of reducing the critical path. .The S-Box is designed using basic gates such as AND gate, NOT gate, OR gate and multiplexer. After designing of s-box based on pipeline architecture then critical path has been decreased and also increased in throughput