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A Case Study on Various Clock Routing Algorithms


Affiliations
1 Department of Electronics and Communication, Marwadi Education Foundation, Rajkot, India
     

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The nature of Clock Tree Synthesis (CTS) in complex hierarchical designs decides timing closure, power dissipation, area of chip and interconnect length. CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize skew and insertion delay. Apart from these, useful skew is also added in the design by means of buffers and inverters. Various clock routing algorithms have been studied in this paper.


Keywords

Clock Tree Synthesis, Physical Design Algorithms, Back-End Design.
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  • A Case Study on Various Clock Routing Algorithms

Abstract Views: 409  |  PDF Views: 2

Authors

Abhishek Parekh
Department of Electronics and Communication, Marwadi Education Foundation, Rajkot, India
Shreyas Charola
Department of Electronics and Communication, Marwadi Education Foundation, Rajkot, India

Abstract


The nature of Clock Tree Synthesis (CTS) in complex hierarchical designs decides timing closure, power dissipation, area of chip and interconnect length. CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize skew and insertion delay. Apart from these, useful skew is also added in the design by means of buffers and inverters. Various clock routing algorithms have been studied in this paper.


Keywords


Clock Tree Synthesis, Physical Design Algorithms, Back-End Design.