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A 30nW Sub-Threshold Adiabatic Carry Look-Ahead Adder in 90nm CMOS
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A sub-threshold adiabatic operation is one of the popular solutions to achieve ultra low power in the realization of modern digital circuits. The proposal of this paper is to design a 4-bit Sub-threshold Adiabatic- Carry Look-Ahead adder (SA-CLA) by utilizing the leakage current as the switching current and the energy stored in the capacitor is recycled instead of discharging it. The proposed SA-CLA has been designed and implemented in 90nm CMOS. The circuit is simulated at different combinations of source voltages and frequencies. The circuit yields a power consumption of 30nW with 400mV supply at 100 KHz.
Keywords
Sub-Threshold Adiabatic-Carry Look-Ahead Adder SA-CLA, Ultra Low Power Consumption, SA-PMOS, SA-NMOS, CADENCE.
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