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Design of a Low-Power & Lower-Delay 8-Bit SRAM Cell Using Pulsed Latch Circuit in 32nm Technology


Affiliations
1 Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India
     

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This paper describes a low-power and lower-delay SRAM (Static Random-Access Memory) Cell using pulsed latch circuit. The delay and power consumption of conventional SRAM Cell is reduced by replacing two NMOS access transistors with pulsed latch circuit. The main aim of the pulsed latch circuit is to reduce delay and increase the speed of the design. As, SRAM Cell is one of the basic building element of VLSI design and due to its huge demand in VLSI chips, it is necessary to reduce power and delay so as to increases the speed of the SRAM Cell. In this paper 1bit, 4bit and 8bit SRAM Cell are designed with pulsed latch circuit and their performance is compared with conventional SRAM Cell design. The conventional SRAM and proposed SRAM Cell, both designs are implemented in 32nm CMOS technology with Vdd = 1.0V in Tanner tool v16.0. In comparision with conventional SRAM Cell the proposed SRAM Cell is much better in terms of power, speed and performance. In the proposed SRAM Cell design delay reduces drastically as compared to that of the conventional SRAM Cell.


Keywords

SRAM Cell, Pulsed Latch Circuit, Speed, Low-Power, Lower-Delay, CMOS Technology, NMOS Access Transistors, 32nm Technology, Tanner Tool.
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  • Design of a Low-Power & Lower-Delay 8-Bit SRAM Cell Using Pulsed Latch Circuit in 32nm Technology

Abstract Views: 253  |  PDF Views: 4

Authors

N. Namrata
Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India
Khemraj Deshmukh
Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India

Abstract


This paper describes a low-power and lower-delay SRAM (Static Random-Access Memory) Cell using pulsed latch circuit. The delay and power consumption of conventional SRAM Cell is reduced by replacing two NMOS access transistors with pulsed latch circuit. The main aim of the pulsed latch circuit is to reduce delay and increase the speed of the design. As, SRAM Cell is one of the basic building element of VLSI design and due to its huge demand in VLSI chips, it is necessary to reduce power and delay so as to increases the speed of the SRAM Cell. In this paper 1bit, 4bit and 8bit SRAM Cell are designed with pulsed latch circuit and their performance is compared with conventional SRAM Cell design. The conventional SRAM and proposed SRAM Cell, both designs are implemented in 32nm CMOS technology with Vdd = 1.0V in Tanner tool v16.0. In comparision with conventional SRAM Cell the proposed SRAM Cell is much better in terms of power, speed and performance. In the proposed SRAM Cell design delay reduces drastically as compared to that of the conventional SRAM Cell.


Keywords


SRAM Cell, Pulsed Latch Circuit, Speed, Low-Power, Lower-Delay, CMOS Technology, NMOS Access Transistors, 32nm Technology, Tanner Tool.

References