Programmable Device Circuits and Systems

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5-Level Cascaded Multilevel Inverter with Reduced Number Switches


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1 BIT, Sathyamangalam, India
     

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Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration.


Keywords

Capacitor Clamped, Diode Clamped, H-Bridge, Multilevel Inverter.
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  • J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverter: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

  • M. Marchesoni and P. Tensa, “Diode-clamped multilevel converters: a practicable way to balance DC-link voltages,” IEEE Trans. Ind. Elec- tron., vol. 49, no. 4, pp. 752–765, Aug. 2002.

  • Y.Chen, B. Mwinyiwiwa, Z. Wolanski, and B.-T.Ooi, “Unified PowerFlow Controller (UPFC) based on chopper stabilized diode-clamped multilevel converters,” IEEE Trans. Power Electron., vol. 15, no. 2, pp.258–267, Mar. 2000.

  • G.Venkataramanan and A. Bendre, “Reciprocity transpositions based sinusoidal pulse width modulation for diode-clamped multilevel converters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1035–1047, Oct.2002.

  • S.Sirisukprasert, J.-S.Lai, and T.-H. Liu, “Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters,”IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 875–881, Aug. 2002.

  • L. M. Tolbert and T. G. Habertler, “Novel multilevel inverter car- rier-based PWM method,” IEEE Trans. Ind. Appl., vol. 35, no. 5, pp.1098–1107, Sep./Oct. 1999.

  • X. Yuan and I. Barbi, “A New Diode Clamping Multilevel Inverter,”IEEE Trans. Power Electron. vol. 15, no. 4, pp. 711–718, Jul. 2000.

  • M. D. Majrekar, P. K. Steimer, and T. A. Lipo, “Hybrid multilevel power conversion system: a competitive solution for high-power appli-cations,” IEEE Trans. Ind. Appl.., vol. 36, no. 3, pp. 834–841, May/Jun.2000.

  • L. M. Tobert, F. Z. Peng, T. Cunnyngham, and J. N. Chiasson, “Charge balance control schemes for cascade multi-level converter in hybrid electric vehicles,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp.1058–1064, Oct. 2002.

  • N. P. Schibli, T. Nguyen, and A. C. Rufer, “A three-phase multilevel converter for high-power induction motors,” IEEE Trans. Power. Electron., vol. 13, no. 5, pp. 978–986, Sep. 1998.

  • F. Z. Peng, J. W. McKeever, and D. J. Adams, “A power line con- ditioner using cascade multilevel inverters for distribution systems,” IEEE Trans. Ind. Appl., vol. 34, no. 6, pp. 1293– 1298, Nov./Dec. 1998.

  • S. Bernet, “Recent developments for high power converter for industryand traction applications,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1102–1117, Nov. 2000.

  • Nagel, S. Bernet, and P. K. Steimer, “A 24 MVA inverter using IGCT series connection for medium voltage applications,” in Proc. IEEE IAS Annu. Meeting, Chicago, IL, Oct. 2001, vol. 2, pp. 867–870.

  • J. Bueno, R. Garcia, M. Marrón, and F. Espinosa, “Modulation Techniques Comparison for Three Levels VSI Converters,” in Proc. IEEE 28th Annu. Conf. Ind. Electron. Soc., Nov. 2002, vol. 2, pp. 908–913.

  • H.du Toit Mouton, “Natural balancing of three-level neutral-point-clamped PWM inverters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1017–1025, Oct. 2002.

  • K. Corzine, X. Kou, and J. R. Baker, “Dynamic average- value mod- eling of four-level drive system,” IEEE Trans. Power. Electron. vol. 18, no. 2, pp. 619–627, Oct. 2003.

  • G. Sinha and T. A. Lipo, “A four-level inverter based drive with a passive front end,” IEEE Trans. Power Electron., vol. 15, no. 2, pp. 285–294, Mar. 2000.

  • E. Soto-Sanchez and T. C. Green, “Voltage balance and control in a multi-level unified power flow controller,” IEEE Trans. Power Delivery, vol. 16, no. 4, pp. 732–738, Oct. 2001.

  • T.Ishida, K. Matsuse, K. Sasagawa, and L. Huang, “Fundamental Characteristics of a Five-Level Double Converter for Induction Motor Drives,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 775–782, Aug.2002.

  • J. von Bloh and R. W. De Doncker, “Control Strategies for Multilevel Voltage Source Converter for Medium-Voltage DC Transmission Sys- tems,” in Proc. 26th Annu. Conf. IEEE Ind. Electron. Soc., Oct. 2000, vol. 2, pp. 1358–1364.

  • Y. Cheng and M. L. Crow, “A Diode-Clamped Multi-Level Inverter for the StatCom/BESS,” in Proc. IEEE PES Winter Meeting, Jan. 2002, vol. 1, pp. 470–475.

  • Tourkhani, P. Viarouge, and T. A. Meynard, “A simulation-opti- mization system for the optical design of a multilevel inverter,” IEEE Trans. Power Electron., vol. 14, no. 6, pp. 1037– 1045, Nov. 1999.

  • K. A. Corzine and X. Kou, “Capacitor voltage balancing in full binary combination schema flying capacitor multilevel inverters,” IEEE Power Electron. Lett., vol. 1, no. 1, pp. 2–5, Mar. 2003.

  • C. Sánchez, F. Ib´ ñez, M. Alcañiz, J. Polo, and R. Masot, “Analysisof Sigma–Delta modulation techniques in low frequency DC– AC con- verters,” in Proc. IEEE 34th PESC’03, Jun. 2003, pp. 507–512.

  • G. Luckjiff, I. Dobson, and D. Divan, “Interpolative Sigma–Delta modulators for high frequency power electronics applications,” in Proc. IEEE PESC’95, Atlanta, GA, Jun. 1995, pp. 444–449.


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  • 5-Level Cascaded Multilevel Inverter with Reduced Number Switches

Abstract Views: 433  |  PDF Views: 2

Authors

C. Geethaa
BIT, Sathyamangalam, India
P. Prem
BIT, Sathyamangalam, India

Abstract


Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration.


Keywords


Capacitor Clamped, Diode Clamped, H-Bridge, Multilevel Inverter.

References