Design of Low Power 45NM Technology Base 11T SRAM Memory

Memory arrays are an essential building block in any digital system. The aspects of designing an SRAM are very vital to designing other digital circuits as well. The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed and reduced layout area. The hope for this project was to be able to create an efficient and compact SRAM. Due to time limitations, the goal was to create a working SRAM design and to learn how the SRAM functions. Design choices were made and justified appropriately. In this paper, a novel Radiation-Hardened-By-Design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology. The verification results obtained confirm that the proposed 11T cell can provide good radiation robustness.