Table of Contents
Vol 10, No 3 (2018)
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Articles
Simulating RAID Using Cacheable Technology | ||
M. Vinoth | ||
Vol 10, No 3 (2018), Pagination: 41-43 | ||
ABSTRACT |
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Abstract Views: 194 | PDF Views: 3 |
A Low Power Threshold Inverter Quantizer Comparator Using Diode Free Adiabatic Logic for 1.2 V, 3-Bit Flash Analog to Digital Converter | ||
Vishal Moyal, Neeta Tripathi | ||
Vol 10, No 3 (2018), Pagination: 44-48 | ||
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Abstract Views: 198 | PDF Views: 3 |
Comparison of Multiplier Design with Various Full Adders | ||
S. Aruna Devi | ||
Vol 10, No 3 (2018), Pagination: 49-53 | ||
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Abstract Views: 204 | PDF Views: 3 |
Building n-bit ADC Using ADC General Cell Architecture in Two Different Configurations with Sample Circuit Implementations | ||
Yasser S. Abdalla | ||
Vol 10, No 3 (2018), Pagination: 54-60 | ||
ABSTRACT |
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Abstract Views: 213 | PDF Views: 3 |