Programmable Device Circuits and Systems

C. Paramasivam ¹, A. Punithavathi ²

Affiliations
1 Department of ECE, K.S. Rangasamy College of Technology, Tiruchengode, Namakkal Dist., Tamil Nadu, IN
2 K.S. Rangasamy College of Technology, Tiruchengode, Namakkal Dist., Tamil Nadu, IN

Abstract

This paper presents Architecture design of a low-power Coarse Grained Reconfigurable Architecture (CGRAs). CGRAs require many Processing Elements (PEs) and configuration cache unit for the reconfiguration of its PE array. The power overhead in configuration cache of CGRA is explicit overhead compared to other types of Intellectual Property cores. In this paper we propose a Reusable Context Pipelining (RCP) to reduce the power overhead in Configuration Cache. The Reusable Context Pipelining architecture reduces the power overhead by using the characteristics of loop pipelining caused by reconfiguration in configuration cache. The power of RAA is compared with normal pipelining architecture structure. The Reconfigurable Array Architecture is designed using Synopsys EDA tool 120nm technology.

Keywords

Coarse Grained Reconfigurable Architecture, Configuration Cache, Loop Pipelining, Reusable Context Pipelining (RCP).

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