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Sahu, Anil Kumar
- A Code Width Built In Self-Test Circuit for Eight Bit Sigma Delta ADC
Authors
1 Department of ETC, SSTC, SSGI (FET), Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 8, No 4 (2016), Pagination: 93-96Abstract
The paper presented here exhibits a modern ADC (analog-to-digital converter) BIST (built-in self test) scheme using code-width with sample difference testing technique. The BIST scheme proposed here is employed on 8-bit sigma-delta ADC which is implemented by using first order oversampling ΣΔ modulator and the decimation filter is second order CIC (Cascaded Integrated Comb) filter. The proposed BIST scheme is certified by simulation of the 8 bit sigma-delta ADC with arbitrary faults. The measurements of Differential Non Linearity (DNL), monotonicity fault and missing code fault have been detected. Power consumed in the proposed BIST circuit is 18mW for the given power supply of 1V. The output is shown at the output of OR gate denoted as 'F'. In order to implement the BIST scheme considered in this paper, an 8 sigma-delta ADC and also the other components were designed in Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology.
Keywords
BIST, BSIM4, Code Width, DNL, Missing Code Fault, Monotonicity Fault.
- A 6.7mW 8-Bit Power Optimzed Sigma-Delta ADC as DUT for Built-in-Self-Test in 45nm CMOS
Authors
1 Department of ETC, Shri Shankaracharaya Technical Campus (SSTC), Bhilai, IN
2 Department of EEE, Chhatrapati Shivaji Institute of Technology, Durg, IN
Source
Programmable Device Circuits and Systems, Vol 8, No 3 (2016), Pagination: 61-66Abstract
Design and testing of oversampling sigma-delta (ΣΔ) Analog to digitals converter is graeat challenge is in todays mixed signal ICs . In this paper a contemporary design for 8-bit ΣΔoversampling ADC is presented, in which first order oversampling ΣΔ modulator and the decimation filter is second order CIC (Cascaded Integrated Comb) filter which is used. Transistor level circuit design and output simulation of the sigma-delta ADC with a power supply of 1V is presented here. This architecture is implemented by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology is used as DUT (design under test )block of Built -in -self -test realization of ADC.
Keywords
8-Bit Sigma-Delta ADC, CIC, Sigma Delta Modulator.- Power-Efficient Montgomery Modular Multiplication Review Using VLSI Architecture
Authors
Source
Programmable Device Circuits and Systems, Vol 10, No 6 (2018), Pagination: 108-112Abstract
In Public key Cryptosystem like RSA and Elliptic Curve Cryptography (ECC), modular multiplication is a basic operation. A famous method to execute modular multiplication in hardware circuit is based on the Montgomery modular multiplication it has several benefits. Many Montgomery Modular multiplication hardware architecture and algorithm employ carry-save addition (CSA), to speed up the encryption/decryption process. An adiabatic logic brings about great deal of power minimization in digital circuit. This research paper presents a review of previous work done on modular multiplication and suggest a new CSA based Montgomery modular multiplier architecture designed utilizing adiabatic logic to make it low power consuming as compare to CMOS-Logic circuit.