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Authors
Affiliations
1 National Institute of Technology, Rourkela, Odisha, IN
2 Department of Computer Science, National Institute of Technology, Rourkela, Odisha-769008, IN
3 Computer Science Engineering Department, National Institute of Technology, Rourkela, Odisha-769008, IN
Source
Programmable Device Circuits and Systems, Vol 6, No 3 (2014), Pagination: 79-83
Abstract
The growing number of cores increases the demand for a powerful memory subsystem. This lead to enhancement in the size of caches in multi-core processors. Caches are responsible in giving processing elements a faster, higher bandwidth local memory to work with. In this paper, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on NIAGRA architecture. The SPLASH-2 benchmark has been used with the simulator Multi2Sim for these experimentations.
Keywords
Cache Configuration, Performance Evaluation, Multi-Core Processor, Performance Enhancement.
