Programmable Device Circuits and Systems

C. Arul Murugan ¹, C. Paramasivam ¹

Affiliations
1 K.S. Rangasamy College of Technology, IN

Abstract

The MPEG-2 is a very popular and widely used compression standard employed in many consumer products such as DVD players and digital cable TV distribution. Basically, the MPEG-2 can be seen as a superset of the MPEG-1 standard. As a part of the recent digital lifestyle movement, demand for mobile digital video continually increases. It was originally developed for digital television, its popularity and effectiveness as a storage/transmission format and abundance of content have made it attractive for use in personal video playback devices. The Inverse Discrete Cosine Transform (IDCT) is a significant component in today’s JPEG and MPEG decoders. Of all the stages in the decoding process of a JPEG file, the IDCT is the most computationally intensive. Hence, we require fast and efficient implementations, either in software or hardware. This feature not only improves the performance of VLD, but also facilitates reducing the power consumption through lowering down the supply voltage. In such mobile devices, energy-efficiency becomes important to battery life, thus motivating the development of an energy efficient audio/video decoder. This paper focus on energy-efficiency by undertaking some framework (by using FPGA).

Keywords

Energy-Efficient, MPEG-2.

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C. Paramasivam ¹, A. Punithavathi ²

Affiliations
1 Department of ECE, K.S. Rangasamy College of Technology, Tiruchengode, Namakkal Dist., Tamil Nadu, IN
2 K.S. Rangasamy College of Technology, Tiruchengode, Namakkal Dist., Tamil Nadu, IN

Abstract

This paper presents Architecture design of a low-power Coarse Grained Reconfigurable Architecture (CGRAs). CGRAs require many Processing Elements (PEs) and configuration cache unit for the reconfiguration of its PE array. The power overhead in configuration cache of CGRA is explicit overhead compared to other types of Intellectual Property cores. In this paper we propose a Reusable Context Pipelining (RCP) to reduce the power overhead in Configuration Cache. The Reusable Context Pipelining architecture reduces the power overhead by using the characteristics of loop pipelining caused by reconfiguration in configuration cache. The power of RAA is compared with normal pipelining architecture structure. The Reconfigurable Array Architecture is designed using Synopsys EDA tool 120nm technology.

Keywords

Coarse Grained Reconfigurable Architecture, Configuration Cache, Loop Pipelining, Reusable Context Pipelining (RCP).

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