A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Sharma, G. K.
- Network-on-Chip Design Space Exploration:A Hybrid Approach
Authors
1 Department of Information Technology, Institute of Management Technology, Nagpur, IN
2 Applied Sciences (Physics) of the Institute, Gwalior, IN
3 ABV Institute of Information Technology and Management, Gwalior, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 7 (2009), Pagination: 197-203Abstract
Network-on-Chip (NoC) has recently emerged as a communication solution for the most System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, we adopted a hybrid approach for design space exploration of a NoC architecture having many-many binding between switches and IP’s. In our proposed methodology, we first mapped the target application onto a 2D mesh NoC architecture using Particle Swarm Optimization (PSO) algorithm to optimize energy consumption. Secondly, we bind the switch and core (IP) using genetic algorithm followed by a routing path allocation using PSO. The results show that our framework optimizes substantially the design matrices like energy,link bandwidth for target applications in compare to other frameworks.