A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
The regular SQRT CSLA consists of two RCA blocks with carry input as 0 and 1.The Final sum will be selected from multiplexers (MUX) by the carry out generated by the pervious block. This paper, proposes an area and delay efficient carry select adder with logical reduction of excess redundant hardware. In the proposed architecture, we had implemented the RCA with carry input as 1, only with MUX, OR gate and AND gate. For 16-bit regular SQRT CSLA there is a reduction of basic logic gates from 434 to 323.The delay is reduced by replacing Full-adder with half-adder in first bit of every RCA in the proposed architecture. This will reduces the number of Iterations required to get the final sum. The proposed architecture shows that there is reduction of area and delay. Based on this architecture, we designed 4-bit,8-bit,16 -bit and 32-bit Square-ischolar_main CSLA (SQRT CSLA) and compared with the regular SQRT CSLA. In this work, we evaluated the performance of the proposed design in 90-ηm CMOS Technology in Xilinx Tools. The result analysis shows that, the proposed SQRT CSLA of 4-bit, 8-bit 16-bit and 32-bit has a reduction of 31.74%, 30.13%, 21.92% and 21.76 % respectively compared with regular SQRT CSLA in area. The delay of Proposed SQRT CSLA of 4-bit,8-bit 16-bit and 32-bit are reduce by 27.47%, 17.23%, 14.32% and 11.63% respectively.
