Programmable Device Circuits and Systems

I. Flavia Princess Nesamani ¹, S. Miriam Niranjana ¹, V. LakshmiPrabha ²

Affiliations
1 Department of Electronics and Communication Engineering, Karunya University, Tamilnadu, IN
2 Government College of Technology, Tirunelveli, Tamilnadu, IN

Abstract

Power is a major concern in today's design. The challenges faced in VLSI (Very Large Scale Integrated) circuits in sub micrometer technologies include increasing power dissipation and interconnect dominance. The pass transistor logic (PTL) family is an excellent choice for low power designs, but its use has been limited due to the lack of design automation tools. The work presents a design for low power and area synthesis. The development of a logic synthesis tool, designed specifically to work with a reduced set cell library consisting of a combination of pass logic and standard CMOS topologies is found to be more advantageous than the conventionally used CMOS logic design styles. Hence hybrid design styles are preferred. The processing technology (0.18um) enables the ease of design. This result in hybrid logic cells for standard cell based design environment.

Keywords

Logic Synthesis, Low Power VLSI, Mentor Graphics, Pass Transistor Logic (PTL), Standard Cell Library.

Full Text

     

I. Flavia Princess Nesamani ¹, K. Mariya Priyadarshini ¹, J. Kanaka Deva Princy ¹, V. Lakshmi Prabha ²

Affiliations
1 Department of Electronics and Communication, Karunya University, Coimbatore 641114, TamilNadu, IN
2 Government College of Technology, Tirunelveli, Tamilnadu, IN

Abstract

The application of general clock skew scheduling is practically limited due to the difficulties in implementing a wide spectrum of dedicated clock delays in a reliable manner. This results in a significant limitation of the optimization potential. As an alternative the application of multiple clocking domains with dedicated clock buffer will be implemented. In this paper, an algorithm for determining the minimum number of clock domains to be used for multi domain clock skew scheduling is presented. The experimental results show the optimized clock period, dynamic power consumption implemented on the traffic light controller.

Keywords

Clock Skew Domain, Clock Skew Scheduling (CSS) Low Power VLSI, Synopsys Design Compiler.

Full Text

     

I. Flavia Princess Nesamani ¹, J. Kanaka Deva Princy ¹, K. Mariya Priyadarshini ¹, V. Lakshmi Prabha ²

Affiliations
1 Department of Electronics and Communication, Karunya University, Coimbatore-641114, TamilNadu, IN
2 Government College of Technology, Tirunelveli, Tamilnadu, IN

Abstract

As device and interconnect dimensions continue to shrink and wafer sizes increase, maintaining process uniformity is increasing in importance. An understanding of variation is essential to control the process and to design manufacturable high-performance circuits. In this paper, a low-cost architectural framework for power performance testing and tuning is developed. It brings the delay and power consumption of a die within the acceptable range. Tuning “knobs” such as tunable gates are employed to deal with delay and power variations. This tuning technique improves the delay yield considerably with minimal impact on area.

Keywords

Control Logic, Low Power VLSI, Mentor Graphics, Tunable Gate.

Full Text