Programmable Device Circuits and Systems

Fazal Noorbasha ¹, S. Dayasagar Chowdary ¹, K. Hari Kishore ¹, Shaik Moulali ¹

Affiliations
1 Department of Electronics & Communication, KL University, Guntur District, IN

Abstract

LFSR's are the functional building blocks of circuits like the pseudo-random noise (PN) code generator that are commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an SR4 (Shift Register) primitive for area-efficient designs LFSR using the encryption and decryption algorithms using XOR gate in 180nm for less area and low power methodologies for ASIC designs using Cadence design tools. The unusual sequence of values generated by an LFSR can be gainfully employed in the encryption and decryption of data. That makes the cryptography quite easy and useful for longer bit lengths. A stream of data bits can be encrypted and decrypted by XOR-ing them with output from an identical LFSR's which finds the certain applications like Radio and visual broad casting schemes, Internet and Wireless communications. This work mainly concentrates on the 4 bit random number that uses for encryption that is mainly works faster clock rates of  100MHz, which finds the application in wireless networks.

Keywords

LFSR, Low Power, CDMA, Pseudo Random Noise Generator, XOR, Encryption and Decryption.

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K. Hari Kishore ¹, Fazal Noorbasha ², Habibulla Khan ³, Asiya Begum ¹, Y. Rajasekhar Reddy , K. Anil Kumar

Affiliations
1 Department of ECE, KL University, Vijayawada, A.P, IN
2 Department of Electronics and Communication Engineering, KL University, Guntur, Andhra Pradesh, IN
3 Department of Electronics & Communication Engineering, KL University, Vijayawada, AP, IN

Abstract

Any VLSI circuit is composed of the very basic unit that is the multiplier. As technology is increasing day by day many new designs are being evolved. As the design becomes bigger more will be the delay in it. If the delay in the basic unit that is multiplier can be decreased then the overall delay in the new designs can be effectively alleviated. There are many multipliers designed so far in the field of VLSI using different methods for its implementation. This paper presents implementation of a Modified Booth multiplier. So far many Modified Booth multipliers are implemented. In all the methods for generating the partial products 'negi' the extra partial product bit is used due to which number of partial products generated will be N/2+1. If this 'negi' bit in the partial products can be avoided and efficient way for generating 2's complement of negative partial product is used which generates conversion signals, and then the number of partial products will decrease to N/2. For addition of partial products the design uses the 4:2 compressors to reduce the complexity in the circuit involved.

Keywords

Modified Booth Multiplier, Partial Product, Conversion Signal, 4:2 Compressors.

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