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Authors
Affiliations
1 Sethu Institute of Technology, IN
2 Department of Electronics and Communication
Engineering, Sethu Institute of Technology, IN
Source
Programmable Device Circuits and Systems, Vol 5, No 4 (2013), Pagination: 167-173
Abstract
A High speed and reduced –area 2D discrete wavelet transform (2D-DWT) architecture is proposed. Previous DWT architecture is mostly based on the modified weighted lifting scheme. In order to achieve a critical path with only one multiplier. Experimental measurement of design performance in terms of area, speed and power for 90nm Complementary Metal Oxide Semiconductor (CMOS) implementation are presented, Results indicate that while BP design exhibit inherent speed advantages.DS design requires significantly fewer hardware resource with increased precision and DWT level.. In addition to the BP and DS design, a novel flexible DWT processor is presented, which supports run time and increase the performance of the DWT parameters .In this proposed approach were give an efficient hardware support to the VLSI architecture achieved by Weighted Lifted Wavelet Transform(WLWT).
Keywords
Fixed Point Arithmetic, Fractional Bit, Image Coding, VLSI, DWT, WLWT, Wavelet Transforms, DSP System Generator.
