Programmable Device Circuits and Systems

M. D. Javeed ¹, B. Hari Krishna ¹, M. V. S. R. Kishore ¹

Affiliations
1 Bomma Institute of Technology, AP, IN

Abstract

The viterbi decoder which is low power with convolution encoder is show in this paper. Convolutional encoding with viterbi decoding is a good forward error correction suitable for channels affected by noise degradation. It is well known that viterbi decoder is dominant module for finding the overall power consumption for the TCM decoders. In this paper we propose an architecture for viterbi decoder with T-algorithm which can effectively reduce the power consumption with a negligible decrease in speed. The operation of searching for the best path metrics in the add-compare-select loop in T-algorithm significantly limits the clock speed. Through optimization at algorithm level greatly shortens the long critical path introduced by the T-algorithm. Implementation result is for code rate ½ with constraint length 9 used for trellis coded modulation. This architecture reduces the power up to 64% without any performance loss when compared with the ideal viterbi decoder, while the degradation in the clock speed is negligible. Xilinx Ise 13.2 tool is used for the synthesization.

Keywords

Convolutional Codes, VLSI, T-Algorithm, Viterbi Decoder, Trellis Coded Modulation (TCM).

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