Programmable Device Circuits and Systems

M. Ponni ¹, Karthikeyan Ramamurthi ², P. R. Vaya ¹

Affiliations
1 ECE Department, Amrita School of Engineering, Bangalore-560035, IN
2 Intel Corporation, ORR, Bangalore, IN

Abstract

Binary addition is the most frequently used and speed limiting operation in the design of data path subsystems. There are several ways to formulate addition operation. Different ways provide different implementations. Among them, parallel prefix adder architectures are very much attractive because of their ease in formulation and implementation efficiency. In this paper, we are presenting the performance evaluation and comparison of 16-bit parallel prefix adder architectures namely Ladner-Fischer, Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. The comparison is done on the basis of three performance parameters i.e. area, power and delay. Out of these adders mentioned above, Han-Carlson architecture is found to be the best compromise.

Keywords

Parallel Prefix Adder, Synopsys.

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