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Tripathi, Neeta
- Comparison of Various Error Detecting Detectors
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Affiliations
1 Department of Electronics & Telecomm. Engg, Shri Shankaracharya Technical Campus-Shri Shankaracharya Institute of Tech & Mgmt, IN
2 Shri Shankaracharya Engineering College, Bhilai, IN
1 Department of Electronics & Telecomm. Engg, Shri Shankaracharya Technical Campus-Shri Shankaracharya Institute of Tech & Mgmt, IN
2 Shri Shankaracharya Engineering College, Bhilai, IN
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Programmable Device Circuits and Systems, Vol 9, No 8 (2017), Pagination: 170-173Abstract
MIMO-OFDM has gained an influential amount of research interest in last 10 years. Although channel estimation and symbol detection is a challenging scenario in MIMO-OFDM because of increased number of transmitter and receiver. Lately, several techniques were used to estimate channels such as maximum likelihood, particle swarm optimization, zero forcing, zero forcing with successive interference cancellation, pilot scheme, pilot multiplexing techniques and differential algorithm. There were few attempts made for solving the problem by metaheuristics approaches, these includes genetic, particle swarm and various other nature-inspired algorithms. The aim of present work is to provide comparison in nine different error detecting detectors and evaluate performance from two parameter signal error rate and computing time.Keywords
Particle Swarm Optimization, Zero Forcing, Maximum Likelihood, Signal Error Rate, Computing Time, Gaussian Tree Approximation.
References
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- A Low Power Threshold Inverter Quantizer Comparator Using Diode Free Adiabatic Logic for 1.2 V, 3-Bit Flash Analog to Digital Converter
Abstract Views :175 |
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Authors
Affiliations
1 Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, Shri Shankaracharya Institute of Tech. & Mgmt. Bhilai, IN
2 Shri Shankaracharya Technical Campus, Shri Shankaracharya Engineering College, Bhilai, IN
1 Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, Shri Shankaracharya Institute of Tech. & Mgmt. Bhilai, IN
2 Shri Shankaracharya Technical Campus, Shri Shankaracharya Engineering College, Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 10, No 3 (2018), Pagination: 44-48Abstract
Diode Free Adiabatic Logic (DFAL) based Threshold Inverter Quantizer (TIQ) is recommended in this paper for implementation of a 3-bit Flash type Analog to Digital Converter. The advised work is simulated with TSMC-65nm Technology on Cadence tool. For appropriate implement of DFAL-TIQ, it is requisite to have a suitable reference voltage for each of the comparator and it is done by accurately sizing the transistors of the comparators. The average power consumed by the advised Flash type ADC when simulated at 100 Hz, 1.2Vpp and for 1fF capacitive load is 5.53 µW, which is 66.03 % lesser than that of the power consumed by Flash ADC containing conventional CMOS-TIQ comparator, and the static parameters observed as: DNL = + 0.56 LSB /-0.61 LSB and INL = +0.40 LSB /-0.43 LSB, respectively.