Programmable Device Circuits and Systems

J. Jeba Priya ¹, M. Annalakshmi ², R. Ganesan ³

Affiliations
1 Department of VLSI Design, Sethu Institute of Technology, Kariapatti-626106, Tamilnadu, IN
2 Department of ECE, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN
3 VLSI Design, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN

Abstract

VLSI architecture of resource efficient the image scaling processor is proposed in this project. The filter combining, hardware sharing, and reconfigurable techniques had been used to reduce hardware cost. This image Scaling Processor consists of a sharpening spatial filter, a clamp filter, bilinear and a nearest neighborhood interpolation. To reduce the blurring and aliasing artifacts produced by the bilinear interpolation, the sharpening spatial and clamp filters are added as prefilters. To minimize the memory buffers and computing resources for the proposed image processor design, a T-model and inversed T-model convolution kernels are created for realizing the sharpening spatial and clamp filters. Compared with previous low-complexity techniques, this architecture requires only a one-line-buffer memory. For achieve more quality images the orthogonal decoder is proposed. This proposed system is designed using verilog HDL, simulated using Modelsim Software and synthesized using Xilinx Project Navigator.

Keywords

Bilinear Interpolation, Clamp Filter, Sharpening Spatial Filter, Reconfigurable Calculation Unit (RCU).

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M. Mohamed Rasik Raja ¹, R. Ganesan ¹

Affiliations
1 Sethu Institute of Technology, Kariapatti, Virudhunagar, Tamilnadu, IN

Abstract

Hough transform is used for detecting circles in an image. To reduce the huge computations in Hough transform, a resource efficient architecture is essential. Resource efficient and reduction in processing time are achieved with data parallelism. We present a circle detection method based on genetic algorithms. Our genetic algorithm uses the encoding of three edge points as the chromosome of candidate circles (x, y, and r) in the edge image of the scene. Fitness function evaluates if these candidate circles are really present in the edge image. Our encoding scheme reduces the search space by avoiding trying unfeasible individuals, this result in a fast circle detector. The implementation of GA-based Hough transform on an FPGA. This architecture is implemented using alter a device at operating frequency of 200MHz. It compute the Hough transform of 512×512 test images with 180 orientation in 2.05 to 3.15ms with minimum number of FPGA resources.

Keywords

Edge Detection, Circle Detection, Genetic Algorithm, Circle Objects Recognition, Mat Lab, Xilinx.

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