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Balamurugan, S.
- Control of Grid Connected PV/Wind Power System
Authors
1 Saveetha School of Engineering, Saveetha University, IN
Source
Programmable Device Circuits and Systems, Vol 7, No 8 (2015), Pagination: 241-244Abstract
In recent year the development t of hybrid renewable energy sources and its application have been studied. In this paper we have focused on hybrid PV/Wind power system and its controller. The hybrid controller has been designed for to maintain the voltage profile at the common connecting point of PV and wind system. The controller has been regulating the voltage profile as per the standard at different environmental conditions. In this paper, we have proposed system has been modelled using Matlab environment and analysis the proposed system results. Finally, simulation results are evaluated and prove the effectiveness of the proposed controller.
Keywords
Hybrid Reewnable Enegry, Photovolatic, Wind, Voltage Regulator.
- A Novel AES VLSI Architecture with Fully-Sub Pipelined Structure for High Throughput and Area Efficiency
Authors
1 School of Electronics Engineering, VIT University, IN
2 School of Electrical Engineering, VIT University, IN
3 School of Information and Technology, VIT, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 7 (2009), Pagination: 183-188Abstract
This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore,composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield (24) are compared. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the keyscheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, a novel architecture was proposed for the fully sub-pipelining is used after each standard round, and sub-pipelined with in the round states, so throughput was increased double to any pipelined architecture. This AES design was implemented using Verilog HDL and synthesized using TSMC’s 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and achieved the through put of 38. 4 Gbps after detailed routing.
Keywords
AES Algorithm, Sub-Pipeline, VLSI, Lookup-Table.- Design and Implementation of Augmented and Advanced Software Stego Archiever System
Authors
1 Department of Computer Science and Engineering, P.S.G. College of Technology, Coimbatore, Tamil Nadu, IN
2 Department of Information Technology, Anna University, Coimbatore, Tamil Nadu, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 3 (2009), Pagination: 47-55Abstract
The objective of the paper is to design and develop a Sotware model Stego Archiver that deals with 4 levels of security in terms of cryptography using RSA algorithm, Compression using Zip algorithm, CRC Checking and Steganography. In addition to these four levels of security, radix 30 method is also employed. Stego Archiver can hide the files in any image formatted file and other multimedia file formats including audio and video files. Stego Archiver is capable of hiding data in any kind of audio files including mp3 files and any kind of video files including mpg, data etc. Since CRC checking is also employed, any attempt to make any changes in original data can be find out easily.