Programmable Device Circuits and Systems

Sushree Sila Panigrahy ¹, Neelam Rup Prakash ¹

Affiliations
1 Electronics and Electrical Engineering Department, PEC University of Technology, Chandigarh-160012, IN

Abstract

In this paper, techniques to build 1-bit full adders using less number of transistors are proposed. New design methodologies for the implementation of XOR and XNOR gates,which are the key components for full adder designs are presented here. This paper discusses two design methodologies for XOR and XNOR gates i.e. 3-T XOR and XNOR gates and Gate-Diffusion-Input (GDI) based XOR and XNOR gates. Two types of full adders are designed, 8-T full adders using 3-T XOR and XNOR gates and 10-T GDI based full adders. The adders are designed using low power technology. Almost all the new proposed adders consume less power as compared to the previously existing full adders due to lesser transistor count and their special structure. They also give improved performance in terms of delay and Power-Delay-Product (PDP), the deciding factors for efficiency measurement of the circuits.

Keywords

3-T XOR, 3-T XNOR, GDI, Full Adders, Delay, Low-Power, High-Speed.

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Sushree Sila Panigrahy ¹, Neelam Rup Prakash ¹

Affiliations
1 Electronics and Electrical Engineering Department, PEC University of Technology, Chandigarh-160012, IN

Abstract

In this paper a CMOS compatible novel Gate Diffusion input (GDI) logic structure is proposed. A novel GDI cell structure is quite similar to a CMOS inverter which has three input ports and one output port. The novel GDI logic is a low power design technique, which enables the implementation of a wide range of logic functions compared to the originally proposed basic GDI cell. This method allows reducing power consumption, delay and area for the design of basic logic gates and few logic functions by using lesser number of transistors than static CMOS logic, while maintaining low complexity of logic design. Logic gates are the basic building blocks for any type of circuit design. So, it is necessary to implement logic gates with minimum power consumption by reducing the transistor count for which novel GDI is a suitable technique to use. A variety of logic gates and functions have been implemented in 1.25 μm CMOS technology. A comparison between static CMOS logic and the proposed novel GDI cell designs has been analyzed. In comparison with conventional static CMOS logic, the novel GDI logic cells achieve reduction in power consumption as well as reduction in power delay product.

Keywords

Gate Diffusion Input (GDI), Logic Functions, Low Power, Static CMOS.

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