Design of Low Power Layered Decoding Architecture for Low Density Parity Check Decoder

Low Density Parity Check (LDPC) Decoder is an iterative decoding process. It requires large amount of memory access which leads to high power consumption. Layered decoding provides efficient and high throughput implementation of LDPC decoders. The row based or column based layered scheduling is introduced to reduce the iteration number. Memory bypassing scheme is proposed to achieve optimal reduction of memory access and to minimize power. Layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. LDPC codes not only exhibit very good error-correcting performance but also effectively fit to partially parallel VLSI decoder implementations.