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Review of Viterbi Decoder and its Adequacy in Digital Communication


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1 Department of ECE, TCST, Bhopal (M.P.), India
     

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Convolutional coding with Viterbi decoding is a powerful method for error correction. It has been widely used in many wireless and satellite communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm is the most commonly used convolutional decoding algorithm. In this research work, a deep research literature work will be done in various journals and articles of Viterbi Decoder. And trying to overcome the issues of noisy signal in satellite receivers by using this reviews. In many articles and journals authors discussed decoding speed, hardware overhead issue, but during long distance digital communication, there is less discussion exist. So for better understating in this review paper, a detailed literature survey is provided on various algorithms used for high speed and less complex design of Viterbi decoders and its decoding techniques and also discussed its hardware overhead of a Viterbi decoder.


Keywords

Convolutional Codes, Viterbi Algorithm, Encoder, Soft Decision, Hard Decision, Path Metric, Branch Metric.
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  • A. J. Viterbi, Convolutional codes and their performance in communication systems. IEEE Transactions on Communication Technology, vol. COM-19, 1971.

  • V. Decoder, B. Raj, M. Reddy, and B. Varalakshmi, “FPGA Based Efficient Implementation of,” International Journal of Computer Engineering In Research Trends, vol. 2, no. 12, pp. 1076–1082, 2015.

  • I. Swathi and S. Rajaram, “FPGA Implementation of Viterbi Decoder for Software Defined Radio Applications,” pp. 2070–2073, 2017.

  • B. Soreng and S. Kumar, “Efficient implementation of Convolution Encoder and Viterbi Decoder,” Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2013, pp. 1270–1273, 2013.

  • K. Cholan, “Design and implementation of low power high speed viterbi decoder,” Procedia Engineering, vol. 30, no. 2011, pp. 61–68, 2012.

  • M. A. Abu, H. Harun, M. Yazdi Harmin, N. I. Abdul Wahab, and M. K. Abdul Kadir, “The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model,” World Journal of Engineering, vol. 13, no. 6, pp. 540–546, 2016.

  • A. J. Mandwale, “Implementation of High Speed Viterbi Decoder using FPGA,” vol. 5, no. 2, pp. 73–77, 2016.

  • S. Mishra and R. R. Tripathi, “VDHL Implementation of Viterbi Algorithm for Decoding of Convolutional Code,” Proceedings - 2015 International Conference on Computational Intelligence and Communication Networks, CICN 2015, no. 1111001, pp. 1367–1370, 2016.

  • V. Kavinilavu, S. Salivahanan, V. S. K. Bhaaskaran, S. Sakthikumaran, B. Brindha, and C. Vinoth, “Implementation of convolutional encoder and Viterbi decoder using Verilog HDL,” ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, vol. 1, pp. 297–300, 2011.

  • A. John, D. Winson, and D. George, “Design and Implementation of Modified Viterbi Decoder for a Wi-Fi Receiver,” pp. 59–64.

  • J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68-73.

  • S. K. Tadse, “DESIGN OF VITERBI DECODER USING HYBRID REGISTER EXCHANGE METHOD,” no. 1, pp. 366–371.

  • D. R. Varma, A. U. Kumar, and B. V. Bhaskar, “Reconfigurable Viterbi Decoder,” vol. 2, no. 5, pp. 124–127, 2012.

  • Y. Y. Liu, X. H. Yang, and D. R. Chen, “The Design of Efficient Viterbi Decoder and Realization by FPGA,” Modern Applied Science, vol. 6, no. 11, pp. 44–48, 2012.

  • S. Shrivastava, “Testing Technique of BIST : A Survey,” vol. 161, no. 3, pp. 22–25, 2017.

  • M. Jabeen and S. Khan, “Design of Convolution Encoder and Reconfigurable Viterbi Decoder,” vol. 1, no. 3, pp. 15–21, 2012.

  • B. Pandita and S. K. Roy, “Design and implementation of a Viterbi decoder using FPGAs,” Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), vol. 147004, no. 6050402.

  • H. Pujara and P. Prajapati, “RTL Implementation of Viterbi Decoder using VHDL,” vol. 2, no. 1, pp. 65–71, 2013


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  • Review of Viterbi Decoder and its Adequacy in Digital Communication

Abstract Views: 186  |  PDF Views: 2

Authors

Atul Deep Soni
Department of ECE, TCST, Bhopal (M.P.), India
Sunil Malviya
Department of ECE, TCST, Bhopal (M.P.), India
Neelesh Gupta
Department of ECE, TCST, Bhopal (M.P.), India

Abstract


Convolutional coding with Viterbi decoding is a powerful method for error correction. It has been widely used in many wireless and satellite communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm is the most commonly used convolutional decoding algorithm. In this research work, a deep research literature work will be done in various journals and articles of Viterbi Decoder. And trying to overcome the issues of noisy signal in satellite receivers by using this reviews. In many articles and journals authors discussed decoding speed, hardware overhead issue, but during long distance digital communication, there is less discussion exist. So for better understating in this review paper, a detailed literature survey is provided on various algorithms used for high speed and less complex design of Viterbi decoders and its decoding techniques and also discussed its hardware overhead of a Viterbi decoder.


Keywords


Convolutional Codes, Viterbi Algorithm, Encoder, Soft Decision, Hard Decision, Path Metric, Branch Metric.

References