International Journal of Advanced Networking and Applications

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Design and Implementation of 64-Bit Ripple Carry Adder and Ripple Borrow Subtractor Using Reversible Logic Gates


Affiliations
1 Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, Bangalore, India
2 Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, RNS Institute of Technology, Bangalore, India
 

Minimal power design is desirable for a range of applications, including the Internet of Things (IoT), quantum computing, and so on. The reversible logic approach is at the foundation of a new technique for designing minimal power digital logic circuits for quantum computing applications. The reversible logic circuit offers a whole new approach to quantum computer processing. Reversible logic gates-based devices will be in high demand for future computer technologies since they require less power. Reversible logic gates were used to design a ripple carry adder (RCA) and a ripple borrow subtractor (RBS), which were simulated in Verilog 2018.3 and coded in Verilog HDL.

Keywords

Constant Inputs, Garbage Outputs, Reversible Logic, Quantum Cost, Ripple Carry Adder (RCA), Ripple Borrow Subtractor (RBS).
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  • Gaur, H. M., Sasamal, T. N., Singh, A. K., Mohan, A., & Pradhan, D., Reversible Logic: An Introduction. Design and Testing of Reversible Logic, Lecture Notes in Electrical Engineering, 2019.

  • Rajput, A. K., Chouhan, S., & Pattanaik, M., Low Power Boolean Logic Circuits using Reversible Logic Gates, International Conference on Advances in Computing, Communication and Contol,2019

  • Anamika, & Bhardwaj, R., Reversible logic gates and its performances,2nd International Conference on Inventive Systems and Control (ICISC),2018.

  • Somani, N., Chaudhary, C., & Yadav, S. Reversible adder design for ripple carry and carry look-ahead adder (4, 8, 16, 32-bit), International Conference on Computing Communication Automation,2016.

  • Kaur, P., & Dhaliwal, B. S., Design fault-tolerant full Adder/Subtractor using reversible gates, International Conference on Computer Communication and Informatics,2012.

  • Kumar, P. K., Rao, P. P., & Kishore, K. H., Optimal design of reversible parity preserving new Full adder / Full subtractor,11th International Conference on Intelligent Systems and Control (ISCO),2017.

  • Thapliyal, H., & Srinivas, M. B., A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Lecture Notes in Computer Science, 2005.

  • Shinde, K. D., & Badiger S., Analysis and comparative study of 8-bit adder for embedded application, International Conference on Control, Instrumentation, Communication and Computational Technologies, 2015.

  • Kotiyal, S., Thapliyal, H., & Ranganathan, Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain, Lecture Notes in Computer Science, 2014.

  • Batish, K., Pathak, S., & Gupta, R. Comparative Analysis for Performance Evaluation of Full Adders Using Reversible Logic Gates, International Conference on Intelligent Circuits and Systems, 2018.

  • Sudhakar J & Padmavani C, A novel ripple borrow subtractor cell design using an asynchronous methodology, International Conference on Inventive Communication and Computational Technologies,2017.


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  • Design and Implementation of 64-Bit Ripple Carry Adder and Ripple Borrow Subtractor Using Reversible Logic Gates

Abstract Views: 217  |  PDF Views: 1

Authors

Hemalatha K N
Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, Bangalore, India
Aishwarya Kamakodi
Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, RNS Institute of Technology, Bangalore, India
A Soppia
Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, RNS Institute of Technology, Bangalore, India
A Poornima
Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, RNS Institute of Technology, Bangalore, India
Sangeetha B G
Department of Electronics & Communication Engineering, Dr. Ambedkar Institute of Technology, RNS Institute of Technology, Bangalore, India

Abstract


Minimal power design is desirable for a range of applications, including the Internet of Things (IoT), quantum computing, and so on. The reversible logic approach is at the foundation of a new technique for designing minimal power digital logic circuits for quantum computing applications. The reversible logic circuit offers a whole new approach to quantum computer processing. Reversible logic gates-based devices will be in high demand for future computer technologies since they require less power. Reversible logic gates were used to design a ripple carry adder (RCA) and a ripple borrow subtractor (RBS), which were simulated in Verilog 2018.3 and coded in Verilog HDL.

Keywords


Constant Inputs, Garbage Outputs, Reversible Logic, Quantum Cost, Ripple Carry Adder (RCA), Ripple Borrow Subtractor (RBS).

References