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Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3D Network on Chip


Affiliations
1 Department of Computer Science and Engineering, ABV-Indian Institute of Information Technology and Management, Gwalior, Madhya Pradesh 474015, India
2 Department of Electrical Engineering, Jabalpur Engineering College, Jabalpur, Madhya Pradesh 482011, India
 

In Network on Chip (NoC) ischolar_mained system, energy consumption is affected by task scheduling and allocation schemes which affect the performance of the system. In this paper we test the pre-existing proposed algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark and has been compared with the existing mapping algorithm spiral and crinkle and has shown better reduction in the communication energy consumption and shows improvement in the performance of the system. On performing experimental analysis of proposed algorithm results shows that average reduction in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%. Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.

Keywords

Network on Chip, Mapping, 3D Architecture, System on Chip, Optimization.
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  • Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3D Network on Chip

Abstract Views: 194  |  PDF Views: 131

Authors

Vaibhav Jha
Department of Computer Science and Engineering, ABV-Indian Institute of Information Technology and Management, Gwalior, Madhya Pradesh 474015, India
Mohit Jha
Department of Electrical Engineering, Jabalpur Engineering College, Jabalpur, Madhya Pradesh 482011, India
G. K. Sharma
Department of Computer Science and Engineering, ABV-Indian Institute of Information Technology and Management, Gwalior, Madhya Pradesh 474015, India

Abstract


In Network on Chip (NoC) ischolar_mained system, energy consumption is affected by task scheduling and allocation schemes which affect the performance of the system. In this paper we test the pre-existing proposed algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark and has been compared with the existing mapping algorithm spiral and crinkle and has shown better reduction in the communication energy consumption and shows improvement in the performance of the system. On performing experimental analysis of proposed algorithm results shows that average reduction in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%. Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.

Keywords


Network on Chip, Mapping, 3D Architecture, System on Chip, Optimization.