Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Implementation and Comparison of Different CIC Filter Structure for Decimation


Affiliations
1 Centre for Advanced Research, Department of Electronics and Communication, Mahendra Engineering College, India
2 Department of Electronics and Communication, Jawaharlal Nehru Technological University, India
     

   Subscribe/Renew Journal


This paper briefs an implementation of different CIC filter architectures for decimation. The different decimation filter structures are implemented using cascaded integrator-comb filter to work for the down sampling ratio of 8. The prototype is designed with MATLAB Simulink model and it is converted to VHDL code using Xilinx system generator. Prototype is implemented in Virtex VXC5VLX110T- 3ff1136 FPGA kit and simulation results and device utilization reports are generated and tabulated. Finally different architectures are compared using number of used LUTs, Registers, Power consumption etc.

Keywords

FPGA – Field Programmable Gate Arrays, SRC - Sampling Rate Conversion, DDC – Digital Down Converter, CIC - Cascaded Integrator Comb Filter.
Subscription Login to verify subscription
User
Notifications
Font Size

Abstract Views: 229

PDF Views: 0




  • Implementation and Comparison of Different CIC Filter Structure for Decimation

Abstract Views: 229  |  PDF Views: 0

Authors

M. Madheswaran
Centre for Advanced Research, Department of Electronics and Communication, Mahendra Engineering College, India
V. Jayaprakasan
Department of Electronics and Communication, Jawaharlal Nehru Technological University, India

Abstract


This paper briefs an implementation of different CIC filter architectures for decimation. The different decimation filter structures are implemented using cascaded integrator-comb filter to work for the down sampling ratio of 8. The prototype is designed with MATLAB Simulink model and it is converted to VHDL code using Xilinx system generator. Prototype is implemented in Virtex VXC5VLX110T- 3ff1136 FPGA kit and simulation results and device utilization reports are generated and tabulated. Finally different architectures are compared using number of used LUTs, Registers, Power consumption etc.

Keywords


FPGA – Field Programmable Gate Arrays, SRC - Sampling Rate Conversion, DDC – Digital Down Converter, CIC - Cascaded Integrator Comb Filter.