Logic Built in Self-Test Verification Statergy for SerDes PHY

VLSI technology has improved rapidly in the past decade. To meet high operating speed, physical layer (PHY) of the system should support high speed communication protocols which made PHY complex. PHY includes Serializer and Deserializer (SerDes), which supports BIST and Loop back as self-testability feature. BIST and Loop back reduces verification time and improves verification quality. Verification strategies for BIST is discussed in this paper. To ensure proper working of BIST module two techniques, BIST flow without error injection and with error injection is presented. Verification flow starts with development of verification plan which is done by V planner. To cover all coverage point from the verification plan, 24 test cases are written. NCSIM simulator is used to run test-cases and analysis. Then regression is run by V manager tool, here in total 49 test cases are run with multiple seeds. For verification of BIST module 100% functional coverage is achieved.