Delay and Power Consumption of Fault Tolerant Data Busses in VDSM Technology

In Very Deep-submicron (VDSM) systems, the scaling of ULSI ICs has increased the sensitivity of CMOS technology to cause various noise mechanisms such as power supply noise, crosstalk noise, leakage noise, etc. In VDSM technology distance between the data bus lines is reduced, so coupling capacitance is dominating factor. Unfortunately, in VDSM systems, the coupling capacitance is of magnitude several times larger than the loading capacitance. The coupling capacitance causes logical malfunction, delay faults, and power consumption on long on-chip data buses. An important effect of the coupling capacitance is Cross talk. Crosstalk is mainly dependent on several factors: drive strength, wire length/spacing, edge rate and propagation duration. The crosstalk noise produces from the coupling capacitance. Such faults may affect data on data bus. To avoid this condition and to guarantee signal integrity on the on-chip communication, a fault tolerant bus can be adopted. This could be achieved by implementing error-correcting codes (ECCs), providing on-line correction and do not require data retransmission. The 4,8,16,and 32-bit data bus is implemented in 180nm, 120nm, and 65nm technologies using Bsim4 model. For reliable transmission of the data ECC techniques is placed on the data bus. We employed a Hamming code and Dual rail as ECC for 4,8,16 and 32-bit fault tolerant data bus. This is implemented in 180nm, 120nm and 65nm technology.