Low Power Highly Optimized Full Adder by Using Different Techniques with 10 Transistors

The Full Adder circuit is an important circuit in application such as Digital Signal Processing (DSP) architecture, microprocessor, and microcontroller and data processing units. This paper discusses the evolution of full adder circuits in terms of lesser power consumption, higher speed. Starting with the most conventional 28 transistor full adder and then gradually studied full adders consisting of as less as 10 transistors. We included some of the most popular full adder cells like Static Energy Recovery Full Adder (SERF), Adder9B, GDI based full adder. In this paper we simulated the 10T Adder using many techniques. The simulation has been carried out on a Microwind environment tool.