TCAM Design Using Parallel Pai-Sigma Matchlines

This work presents a Parallel Pai-Sigma matchline to reduce the compare (search) power of a ternary content addressable memory (TCAM). The pai-sigma matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid NAND-NOR matchline. The switching activity of the search lines of a TCAM with the pai-sigma matchlines is low. We have implemented the low-power TCAM using CMOS 180nm, 120 and 65nm technologies in microwind3.1cadtool. The parallel pai-sigma matchline, When the technology scale down from 180nm to 65nm, power is 1.507μw, delay decreased from 8.566ns to 0.236ns and power-delay product varies from 12.908 to 0.355x10^-15 W-s. Ternary content addressable memory (TCAM) is an important component for many applications. For TCAM-based networking systems, the rapidly growing size of routing tables brings with it the challenge to design higher search speeds and lower power consumption.