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Authors
Affiliations
1 Department of ECE, REVA ITM, Bangalore, IN
Source
International Journal of Engineering Research, Vol 5, No SP 5 (2016), Pagination: 1030-1032
Abstract
This paper presents an improved design of phase frequency detector for Phase Locked Loop (PLL), which retains the main characteristics of PFD. The proposed design uses 18 transistors operated at 1.8V power supply and it consumes power of 42.7uW when reference input frequency clock operates at 400MHz. The dead zone has been completely eliminated. The design is implemented in cadence virtuoso using gpdk180nm CMOS process technology.
Keywords
Dead Zone, PFD, PLL.
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