International Journal of Engineering Research

M. Anitha ¹, J. Princy Joice ¹, I. Rexlin Sheeba ¹

Affiliations
1 Dept. of ECE, Sathyabama University, Chennai, Tamilnadu, IN

Abstract

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder. The proposed method aims on GDI (Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder. This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence,the proposed architecture mainly concentrating on the area level & reducing the power using modified GDI logic.

Keywords

Fast Adder, Modified GDI, Low Power Design.

Full Text