International Journal of Engineering Research

M. Mahesh Kumar ¹, N. Chandra Sekhar ¹

Affiliations
1 Department of ECE., ACET, Allagadda, IN

Abstract

In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power-delay-product metrics are 22.7% and 29.7%, respectively.

Keywords

Flip-Flop (FF), Low Power, Pulse-Triggered.

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