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Authors
Affiliations
1 Department of ECE, Annamacharya Institute of Technology & Sciences (Autonomous), Rajampet, Kadapa (Dt.), IN
Source
International Journal of Engineering Research, Vol 3, No SP 2 (2014), Pagination: 73-76
Abstract
Now a days there is an ever growing demand for high speed processing and low area design. It is known fact that the multiplier unit forms an integral part of processor design. Due to this, high speed multiplier architectures become the need of the day. Here, we introduce the architecture that to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is available.
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