International Journal of Engineering Research

U. Sudha Rani ¹, S. P. Suresh Naik ¹

Affiliations
1 E.C.E Department (VLSI & ESD), GATES Institute of Technology, Gooty, IN

Abstract

Low-cost finite impulse response (FIR) esigns are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Non-uniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR design approaches show that the proposed designs achieve the best area and power results.

Keywords

Digital Signal Processing (DSP), Faithful Rounding, Finite Impulse Response (FIR) Filter, Truncated Multipliers, VLSI Design.

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