International Journal of Engineering Research

Khandaker Mohammad Raisul Amin ¹, Tongxi Wang ¹, Min-Woong Seo ¹, Shoji Kawahito ¹

Affiliations
1 Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Naka-ku, Hamamatsu 432-8011, JP

Abstract

This paper presents a technique for digital error correction of the non linearity due to capacitor mismatch and finite gain error of operational amplifier in the first-order resettable delta-sigma modulator (RDSM) used in a multiple-sampling based high-resolution ADC. The effectiveness of the digital error correction is confirmed by using circuit simulation data with 65 nm technology parameters. The simulation results show that the digital error correction improves the integral non linearity (INL) from +4.52/-4.58 LSB to +0.30/-0.45 LSB at 12 bits.

Keywords

Resettable Delta-Sigma Modulator, Digital Error Correction.

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