Design of Efficient Two Stage Power Amplifier Using 65nm Cmos Technology

In the modern Era, VLSI design is one of the paradigm to have low noise,high power and small chip area. The design of CMOS power amplifier is an effort in this domain which is applicable for wireless communication system. The proposed design employ switching mode of two stage power amplifier to exploit it’s soft switching property to achieve high output power and high efficiency.

Two stage power amplifier for WLAN applications in 65nm CMOS technology is proposed to be designed. The functionality of proposed design of two stage power amplifier will be verified for parameters like high output power and high efficiency. The main emphasis is on achieving high gain with low return losses.

The layout of the proposed power amplifier will be tried to have minimum design area with improved parameters as compared to previous literature reviewed designs.