Novel 16-Bit Adder Design For Low Power, Area And Delay

Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumption. The Novel 16-Bit Adder is designed 16-bit and then compared with conventional CSA respective architectures. Novel Adder shows reduction in Delay, Area and Power consumption in comparison with conventional CSA.

In this paper, by using Novel 16-Bit  architecture to reduce Delay, Area and Power. The MCSA is designed by using single RCA and Binary to Excess-1 Converter (BEC) instead of using dual RCAs.