Real Time Design & Implementation Of Digital Speedometer On FPGA

 In this paper, a Digital Speedometer is designed and implemented using FPGA (Field Programmable Gate Array). Here, the FPGA used is Smart Fusion FPGA. It is more flexible in hardware and embedded design where need a true system-on-chip (SoC) solution FPGA devices are ideal than traditional fixed-function microcontrollers and without the excessive cost of soft processor cores on traditional FPGAs. At the inception, the speedometer is designed using Verilog Hardware Description Language. Synthesis-software algorithmically transforms the Verilog source code into a netlist, a logically-equivalent description consisting only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific FPGA or VLSI technology. The designed speedometer gives lots of extra features than existing speedometers. The special addition of this speedometer is the velocity of the speedometer is accurate not only in normal times but also at exceedingly small velocities.