Design Of Area Optimized Aes 128 Algorithm Using Mixcolumn Transformation

In cryptography, the Advanced Encryption Standard (AES), also known as Rijndael, is a block chiper adopted as an encryption standard. Rijndael is an encryption algorithm that has been designed with the state of art in the cryptographic research and is still believed very secure by most of the people. The algorithm accepts blocks of size 128, 192, or 256 bits. Independently, the key length can be 128, 192, or 256 bits as well. All encryptions are done in a certain number of rounds, which varies between 10, 12, and 14, and it depends on the size of the block length and the key length chosen. An encryption module is used to generate all the intermediate encryption data, and a separate key-scheduling module is used to generate all the sub-round keys from the initial key. The project is intended to design and implement AES algorithm and to maximize the encryption throughput while minimizing the area consumption at the same time maximizing the throughput will minimize the critical paths and solve the memory access conflicts. The VHDL code can be simulated to verify its functionality. Then gate level design equivalent will be synthesized targeting FPGA. Xilinx software is used for Design Entry, Simulation and Synthesis.