A Novel Poly-Phase Architecture For High Performance Discrete Wavelet Transform In FPGA

Wavelet Transforms are used in number of application. They are applied in different fields such as signal processing, speech and image compression, biometrics, and so on. Design of discrete wavelet transforms is complex due to large number of arithmetic operations involved. In this Paper, pipeline VLSI architecture for the computation of the 1-D discrete wavelet transform (DWT) using poly-phase filter bank structure is proposed. The main focus of the scheme is on reducing the number and period of clock cycles and reducing the complexity of hardware resources needed for the computation. For hardware implementation, the choice of filter bank structure determines the efficiency and accuracy of computation of the DWT. here poly-phase filter bank structure is proposed for DWT computation which increases performance of computation as in poly-phase implementation units can operate in parallel, and therefore the filtering operation have less delay and however, pipelining can be used in this scheme to reduce the delay.