Implimentation of Clocked Pair Shared Flip-Flop for Low Power Applications by Double Edge Triggering Techniques

Power consumption is the most important aspect in regards to system performance. This project focus on low power clocking methods to reduce the power consumption in chips and flip-flops by reducing the number of clocked transistors used in it. 40% of the clocked transistors are reduced by using Clocked Pair Shared Flip-Flops [CPSFF]. This would be able to reduce 24% of the clock driving power in most of the SOC. In addition to this low swing and double edge clocking can be used to build clocking system.A simple transistor DET design is used to reduce the leakage current. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS 180nm technology is use in SPICE tool to design the proposed structure.